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pin configurations 8-lead narrow body so (so-8) op250 out a ?n a +in a v out b ?n b +in b v+ 1 2 3 4 8 7 6 5 (not to scale) 8-lead tssop (ru-8) ?n a +in a v out b ?n b +in b v+ 1 4 5 8 out a op250 14-lead narrow body so (n-14) out a ?n a +in a v+ ?n d +in d v out d 1 2 3 4 14 13 12 11 +in b ?n b out b ?n c out c +in c 5 6 7 10 9 8 op450 (not to scale) 14-lead tssop (ru-14) ad8532 out a ?n a +in a v+ ?n d +in d v out d 1 14 +in b ?n b out b ?n c out c +in c 78 op450 1 14 78 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a cmos single-supply rail-to-rail input/output operational amplifiers op250/op450 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1997 features single-supply operation: 2.7 v to 6 v high output current: 6 100 ma low supply current: 800 m a/amp wide bandwidth: 1 mhz slew rate: 2.2 v/ m s no phase reversal low input currents unity gain stable applications battery powered instrumentation medical remote sensors asic input or output amplifier automotive general description the op250 and op450 are dual and quad cmos single-supply, amplifiers featuring rail-to-rail inputs and outputs. both are guar- anteed to operate from a +2.7 v to +5 v single supply. these amplifiers have very low input bias currents. outputs are capable of driving 100 ma loads and are stable with capacitive loads. supply current is less than 1 ma per amplifier. applications for these amplifiers include portable medical equipment, safety and security, and interface to transducers with high output impedance. the ability to swing rail-to-rail at both the input and output en- ables designers to build multistage filters in single-supply sys- tems and maintain high signal-to-noise ratios. the op250 and op450 are specified over the extended indus- trial (C40 c to +125 c) temperature range. the op250, dual, is available in 8-lead tssop and so surface mount packages. the op450, quad, is available in 14-lead thin shrink small out- line (tssop) and narrow 14-lead so packages.
rev. 0 C2C op250/op450Cspecifications electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage v os 8mv C40 c < t a < +125 c20mv input bias current i b 240 pa C40 c < t a < +85 c60pa C40 c < t a < +125 c 500 pa input offset current i os 0.5 25 pa C40 c < t a < +125 c60pa input voltage range 03v common-mode rejection ratio cmrr v cm = 0 v to 3 v 40 55 db C40 c < t a < +125 c35 db large signal voltage gain a vo r l = 2 k w , v o = 0.3 v to 2.7 v 800 v/mv offset voltage drift d v os / d t10 m v/ c bias current drift d i b / d t 1.8 pa/ c offset current drift d i os / d t 0.07 pa/ c output characteristics output voltage high v oh i l = 100 m a 2.99 v i l = 10 ma 2.85 2.94 v C40 c to +125 c 2.8 v output voltage low v ol i l = 100 m a1mv i l = 10 ma 55 100 mv C40 c to +125 c 125 mv output current i out 100 ma open loop impedance z out f = 1 mhz, a v = 1 180 w power supply power supply rejection ratio psrr v s = 2.7 v to 6 v 60 80 db C40 c < t a < +125 c55 db supply current/amplifier i sy v o = 0 v 700 1,000 m a C40 c < t a < +125 c 1,250 m a dynamic performance slew rate sr r l = 10 k w 1.9 v/ m s settling time t s to 0.01% 4 m s gain bandwidth product gbp 0.95 mhz phase margin ?o 46 degrees channel separation cs f = 1 khz, r l = 10 k w 100 db noise performance voltage noise e n pCp 0.1 hz to 10 hz 10 m v pCp voltage noise density e n f = 1 khz 45 nv/ ? hz f = 10 khz 30 nv/ ? hz current noise density i n f = 1 khz 0.05 pa/ ? hz specifications subject to change without notice. (v s = 1 3.0 v, t a = 1 25 8 c, v cm = 1.5 v unless otherwise noted)
electrical characteristics parameter symbol conditions min typ max units input characteristics offset voltage v os 2 7.5 mv C40 c < t a < +125 c20mv input bias current i b 240 pa C40 c < t a < +85 c60pa C40 c < t a < +125 c 500 pa input offset current i os 0.5 25 pa C40 c < t a < +125 c60pa input voltage range 05v common-mode rejection ratio cmrr v cm = 0 v to 5 v 45 60 db C40 c < t a < +125 c40 db large signal voltage gain a vo r l = 2 k w , vo = 0.3 v to 4.7 v 1,000 v/mv offset voltage drift d v os / d t C40 c < t a < +125 c10 m v/ c bias current drift d i b / d t 1.8 pa/ c offset current drift d i os / d t 0.07 pa/ c output characteristics output voltage high v oh i l = 100 m a 4.99 v i l = 10 ma 4.9 4.94 v C40 c to +125 cmv output voltage low v ol i l = 100 m a1v i l = 10 ma 40 100 mv C40 c to +125 c 125 mv output current i out 100 ma open loop impedance z out f =1 mhz, a v = 1 200 w power supply power supply rejection ratio psrr v s = 2.7 v to 6 v 60 80 db C40 c < t a < +125 c55 db supply current/amplifier i sy v o = 0 v 800 1,250 m a C40 c < t a < +125 c 750 1,750 m a dynamic performance slew rate sr r l = 10 k w 2.2 v/ m s full-power bandwidth bw p 1% distortion 100 khz settling time t s to 0.01% 3 m s gain bandwidth product gbp 1 mhz phase margin ?o 48 degrees channel separation cs f = 1 khz, r l = 10 k w 100 db noise performance voltage noise e n pCp 0.1 hz to 10 hz 10 m v pCp voltage noise density e n f = 1 khz 45 nv/ ? hz f = 10 khz 30 nv/ ? hz current noise density i n f = 1 khz 0.05 pa/ ? hz specifications subject to change without notice. rev. 0 C3C op250/op450 (v s = 1 5.0 v, t a = 1 25 8 c, v cm =2.5 v unless otherwise noted)
op250/op450 rev. 0 C4C package type u ja * u jc units 8-lead soic (s) 158 43 c/w 8-lead tssop (ru) 240 43 c/w 14-lead soic (n) 120 36 c/w 14-lead tssop (ru) 180 35 c/w * q ja is specified for the worst case conditions, i.e., q ja specified for device soldered in circuit board for surface mount packages. absolute maximum ratings 1, 2 supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 v input voltage 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd to v s common-mode input voltage . . . . . . . . . . . . . . . . . . . . 6 v output short-circuit duration to gnd . . . . . . . . . . . . . observe derating curves esd susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 v storage temperature range s, ru package . . . . . . . . . . . . . . . . . . . . . 2 65 c to +150 c operating temperature range op250g/op450g . . . . . . . . . . . . . . . . . . 2 40 c to +125 c junction temperature range s, ru package . . . . . . . . . . . . . . . . . . . . . 2 65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . +300 c notes 1 absolute maximum ratings apply at +25 c, unless otherwise noted. 2 stresses above those listed under absolute maximum ratings may cause perma - nent damage to the device. this is a stress rating only; the functional operation of the device at these or any other conditions above those indicated in the opera tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the op250/op450 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide temperature package package model range description options op250gs C40 c to +125 c 8-lead soic so-8 op250gru C40 c to +125 c 8-lead tssop ru-8 OP450GS C40 c to +125 c 14-lead soic n-14 op450gru C40 c to +125 c 14-lead tssop ru-14 warning! esd sensitive device
load current ?ma 10k 10 0.1 0.001 100 0.01 output voltage ?mv 0.1 1 10 1 100 1k source sink v s = +2.7v t a = +25
temperature ?
op250/op450 rev. 0 C7C frequency ?hz 400 350 0 10k 100k impedance ?
25mv 2? v s =
op250/op450 rev. 0 C9C 200nv 30nv/
op250/op450 rev. 0 C10C output phase reversal the opx50 is immune to output voltage phase reversal with an input voltage within the supply voltages of the device. however, if either of the devices inputs exceeds 0.6 v outside of the sup- ply rails, the output could exhibit phase reversal. this is due to the esd protection diodes becoming forward biased, thus caus- ing the polarity of the input terminals of the device to switch. the technique recommended in the input overvoltage protec- tion section should be applied in applications where the possibil- ity of input voltages exceeding the supply voltages exists. output short circuit protection to achieve high quality rail-to-rail performance, the outputs of the opx50 family are not short-circuit protected. although these amplifiers are designed to sink or source as much as 250 ma of output current, shorting the output directly to ground could damage or destroy the device when excessive volt- ages or currents are applied. if to protect the output stage, the maximum output current should be limited to 250 ma. by placing a resistor in series with the output of the amplifier as shown in figure 28, the output current can be limited. the minimum value for r x can be found from equation 2. r v ma x sy 3 250 (2) for a +5 v single supply application, r x should be at least 20 w . because r x is inside the feedback loop, v out is not af- fected. the trade-off in using r x is a slight reduction in output voltage swing under heavy output current loads. r x will also increase the effective output impedance of the amplifier to r o + r x , where r o is the output impedance of the device. theory of operation the opx50 family of amplifiers are cmos rail-to-rail input and output single supply amplifiers designed for low cost and high output current drive. these features make the opx50 op amps ideal for multimedia and telecom applications. figure 27 shows the simplified schematic for an opx50 ampli- fier. two input differential pairs consisting of an n-channel pair (m1Cm2) and a p-channel pair (m3Cm4) provide a rail-to-rail input common-mode range. the outputs of the input differen- tial pairs are combined in a compound folded-cascode stage, which drives the input to a second differential pair gain stage. the outputs of the second gain stage provide the gate voltage drive to the rail-to-rail output stage. the rail-to-rail output stage consists of m15 and m16, which are configured in a complementary common-source configura- tion. as with any rail-to-rail output amplifier, the gain of the output stage, and thus the open loop gain of the amplifier, is de- pendent on the load resistance. also, the maximum output volt- age swing is directly proportional to the load current. the difference between the maximum output voltage to the supply rails, known as the dropout voltage, is determined by the opx50s output transistors on-channel resistance. the output dropout voltage is given in figures 1 and 2. input voltage protection although not shown on the simplified schematic, there are esd protection diodes connected from each input to each power supply rail. these diodes are normally reversed biased, but will turn on if either input voltage exceeds either supply rail by more than 0.6 v. should this condition occur the input current should be limited to less than 5 ma. this can be done by placing a resistor in series with the input. the minimum resistor value should be: r v ma in in max 3 , 5 (1) v ee v cc v out Cv in +v in m1 m2 m3 m4 bias m5 m6 bias bias figure 27. opx50 simplified schematic
op250/op450 rev. 0 C11C +5v r x 20
op250/op450 rev. 0 C12C be connected from the output to ground in parallel with the ca- pacitive load as shown in figure 33. the proper snubber net- work on the output can significantly reduce output overshoot, although it will not increase the bandwidth. table i shows some snubber network values for a given capacitive load. in practice, these values are best determined empirically based on the exact capacitive load for the application. +5v r s 5
op250/op450 rev. 0 C13C 1/2 op250 20
op250/op450 rev. 0 C14C * op250 spice macro-model typical values * 10/97, ver. 1 * tam / adsc * * node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * |||| output * ||||| * ||||| .subckt op250 1 2 99 50 45 * * input stage * m1 4 3 6 6 mnin l=2u w=66u m2 5 2 6 6 mnin l=2u w=66u m3 7 3 9 9 mpin l=2u w=66u m4 8 2 9 9 mpin l=2u w=66u rd1 99 4 5e3 rd2 99 5 5e3 rd3 7 50 5e3 rd4 8 50 5e3 vcm1 10 50 -.3 vcm2 99 11 -.3 d1 10 6 dx d2 9 11 dx eos 3 1 poly(3) (61,98) (73,98) (81,0) 3e-3 +1 1 1 ios 1 2 .25e-12 ibias1 6 50 700e-6 ibias2 99 9 700e-6 * * cmrr=60 db, zero at 20khz * ecm1 60 98 poly(2) (1,98) (2,98) 0 .5 .5 rcm1 60 61 159.2e3 rcm2 61 98 159 ccm1 60 61 50e-12 * * psrr=90db, zero at 200hz * rps1 70 0 1e6 rps2 71 0 1e6 cps1 99 70 1e-5 cps2 50 71 1e-5 epsy 98 72 poly(2) (70,0) (0,71) 0 1 1 rps3 72 73 1.59e6 cps3 72 73 500e-12 rps4 73 98 50 * * internal voltage reference * rsy1 99 91 100e3 rsy2 50 90 100e3 vsn1 91 90 dc 0 eref 98 0 (90,0) 1 gsy 99 50 poly(1) (99,50) -1.81e-3 1.5e-5 * * voltage noise reference of 30nv/rt(hz) * vn1 80 0 0 rn1 80 0 16.45e-3 hn 81 0 vn1 30 rn2 81 0 1 * * pole at 1.25mhz * g2 98 20 poly(2) (4,5) (7,8) 0 5e-5 5e-5 r2 20 98 10e3 c2 20 98 12.7e-12 * * gain stage * g1 98 30 (20,98) 3.5e-4 r1 30 98 6.25e6 cf 30 45 135e-12 d4 31 99 dx d5 50 32 dx v1 31 30 0.7 v2 30 32 0.7 * * output stage * m5 45 41 99 99 mpout l=2u w=6660u m6 45 42 50 50 mnout l=2u w=6660u eo1 99 41 poly(1) (98,30) .9232 1 eo2 42 50 poly(1) (30,98) .8914 1 * * models * .model mnin nmos(level=2,vto=0.75, +kp=20e-6,cgso=0,kf=2.5e-31,af=1) .model mpin pmos(level=2,vto=-0.75, +kp=20e-6,cgso=0,kf=2.5e-31,af=1) .model mnout nmos(level=2,vto=0.75, +kp=30e-6,lambda=0.04,cgso=0) .model mpout pmos(level=2,vto=-0.75, +kp=20e-6,lambda=0.04,cgso=0) .model dx d(is=1e-16) .ends op250
op250/op450 rev. 0 C15C outline dimensions dimensions shown in inches and (mm). 8-lead soic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 14-lead plastic dip (n-14) 14 17 8 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) pin 1 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 8-lead tssop (ru-8) 8 5 4 1 0.122 (3.10) 0.114 (2.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.0256 (0.65) bsc seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 14-lead tssop (ru-14) 14 8 7 1 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0
c3236C8C10/97 printed in u.s.a. C16C

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